1. Field of the Invention
This invention generally relates to methods and systems to adjust the refresh rates for a semiconductor memory. More specifically, the invention relates to such methods and systems that are based on adjusting the refresh rates as a function of the cell leakage rates of the semiconductor memory.
2. Prior Art
Semiconductor memory such as dynamic random access memory or DRAM components are utilized extensively for an inexpensive solid state storage medium for digital devices such as personal computers, cellular telephones, personal data assistants and countless other products on the market today. Digital information, in the unit of one bit, resides as a single charge stored in a two dimensional array of capacitors, each having an associated transistor. Typically a one megabit memory would have 1024×1024 memory cells. A single memory cell within the 1024 can be selected by a 10-bit row address and a 10-bit column address. The memory cells, due to the charge leakage inherent in the capacitor-transistor pair, require constant refreshing, which forms the basis of the present invention.
Charges stored in the cells discharge or dissipate over time, which require that they be recharged to retain the charge levels corresponding to the value of the data they hold. There are many leakage paths for a storage capacitor such as leakage through the device's diffusion junctions and transfer gate channels dependent upon temperature, process variations (e.g., wafer to wafer fabrication, channel lengths, the threshold voltages, junction implant), and system voltage fluctuations. As temperature and voltage fluctuate during the operation of the digital device, refresh rate control can be become critical to the sound operation of the DRAM.
The circuitry for performing recharging or refresh operations can be external or internal to the memory. In an internal refresh process, both the time base and refresh row address counter are internal to the DRAM. In order to work properly, timing and refresh signals need to be provided in certain sequences and remain active during specified periods.
In U.S. Pat. No. 6,483,764 Chen Hsu, et al. teaches a method of using a DRAM refresh method and system and a method of designing a low-power leakage monitoring device. With the DRAM refresh method, the time is adjusted based on the cell leakage condition. The '764 method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the memory array. The monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The system is step-wise variable, whereby the refresh rate increases or decreases occurs in fixed steps. Neither the '764 method nor the corresponding system teaches the use of a sensing circuit that provides a continuously variable refresh rate by essentially tracking the influences of process, temperature and voltage variations on the memory cell leakage condition.